Conventional complementary metal-oxide-semiconductor (CMOS) devices offer higher on-current for n-type field effect transistors (NFETs) than for p-type field effect transistors (PFETs) having similar physical dimensions. This is, in general, due to higher electron mobility than hole mobility in most semiconductor materials. In the case of a silicon substrate having a (100) surface, the ratio of electron mobility to hole mobility is about 2. Correspondingly, semiconductor circuits have been designed to factor in the differences in the on-current per unit width of NFETs and PFETs.
Static random access memory (SRAM) is a memory device employing six transistors. SRAM cell design typically begins by picking the smallest PFET supported by a given technology for two pull-up PFETs, followed by scaling of NFET pass gate transistors and pull-down NFET transistors for optimal beta ratio, cell stability, and access time.
Referring to FIGS. 1A-1C, an exemplary prior art SRAM cell structure comprises a first planar pull-up PFET 116, a second planar pull-up PFET 116′, two planar pull-down NFETs (114, 114′), and two planar pass gate NFETs (112, 112′). FIG. 1A is a top-down view of the exemplary SRAM cell up to the CA level not showing a middle-of-line (MOL) dielectric 170. FIG. 1B is a vertical cross-sectional view of the exemplary SRAM cell along the plane B-B′ showing the MOL dielectric 170. FIG. 1C is a vertical cross-sectional view of the exemplary SRAM cell along the plane C-C′ showing the MOL dielectric 170. Each of the transistors (112, 112′, 114, 114′, 116, 116′) comprise a portion of the semiconductor substrate 110, a portion of a gate dielectric 130, a portion of gate electrodes 132, portions of gate spacers 134, portions of active area (AA) silicides 160, and a portion of gate top silicides 164.
The gate dielectric 130 may comprise a conventional semiconductor oxide based dielectric material such as silicon oxide or silicon nitride. Alternately, the gate dielectric 130 may comprises a high dielectric constant (high-k) material having a dielectric constant greater than 4.0, and typically greater than 7.0. The gate electrodes 132 may comprise a doped polycrystalline semiconductor material such as doped polysilicon. Alternately, the gate electrodes 132 may comprise a metal gate material known in the art.
A shallow trench isolation structure 120 physically separates the transistors (112, 112′, 114, 114′, 116, 116′) and provides electrical isolation among the transistors (112, 112′, 114, 114′, 116, 116′). CA contact vias 176 and CA bars 178 are employed to provide electrical wiring among the transistors (112, 112′, 114, 114′, 116, 116′). One of the CA bars 178, which contacts one of the AA silicides 160 of the first planar pull-up PFET 116 as well as the gate top silicides 164 of the second planar pull-up PFET 116′ as shown in FIG. 1B, provides electrical connection between the drain of the first planar pull-up PFET 116 and the gate of the second planar pull-up PFET 116′. Likewise, another CA bar 178 provides electrical connection between the drain of the second planar pull-up PFET 116′ and the gate of the first planar pull-up PFET 116.
Each of the active areas for the planar pass gate NFETs (112, 112′) has a first width W1, and each of the active areas for the planar pull-down NFETs (114, 114′) has a second width W2. A beta ratio, which is the ratio of an on-current of each of the planar pull-down NFETs (114,114′) to an on-current of each of the planar pass gate NFETs (112, 112′), is substantially the same as the ratio of the second width W2 to the first width W1. Typically, the planar pass gate NFETs (112, 112′) and the planar pull-down NFETs (114, 114′) have the same threshold voltage. It has been shown that the beta ratio needs to be close to 2.0 for optimal cell stability of an SRAM cell. Thus, the ratio of the second width W2 to the first width W1 is close to 2.0 in the exemplary prior art SRAM cell.
Referring to FIGS. 2A-2C, the exemplary SRAM cell is shown up to an M1 level, which is a first metal interconnect level. FIG. 2A is a top-down view of the exemplary SRAM cell up to the M1 level. The middle-of-line (MOL) dielectric 170 and an M1 dielectric 180 are not shown in FIG. 2A. FIG. 2B is a vertical cross-sectional view of the exemplary prior structure along the plane B-B′ showing the MOL dielectric 170 and the M1 dielectric 180. FIG. 2C is a vertical cross-sectional view of the exemplary SRAM cell along the plane C-C′ showing the MOL dielectric 170 and the M1 dielectric 180. M1 wires 188 embedded within the M1 dielectric 180 contact the underlying CA contact vias 176 and the CA bars 178. In the exemplary prior art SRAM cell, the drain of each of the two planar pull-up transistors (116, 116′) is electrically connected to a node at which a source/drain of one of the planar pass gate transistors (112, 112′) adjoins the drain of one of the planar pull-down NFETs (114, 114′) by a combination of a CA bar 178, an M1 wire 188, and a CA contact via 176. Two such combinations are present in each SRAM cell structure which comprises six transistors (112, 112′, 114, 114′, 116, 116′).
Referring to FIG. 3, a circuit schematic 118 for the exemplary prior art SRAM cell shows a first pair of a first pass gate n-type field effect transistor (NFET) 102 and a first pull-down n-type field effect transistor (NFET) 104. A first source/drain of the first pass gate NFET 102 and a first drain of the first pull down NFET 104 are adjoined to form an electrical connection. In the physical structure, this electrical connection is achieved by a first common active area that contains both the first source/drain of the first pass gate NFET 102 and the first drain of the first pull-down NFET 104. Similarly, a second source/drain of the second pass gate NFET 102′ and a second drain of a second pull-down NFET 104′ are adjoined to form another electrical connection. In the physical structure, this electrical connection is achieved by a second common active area that contains both the second source/drain of the second pass gate NFET 102′ and the second drain of the second pull-down NFET 104′. The circuit schematic 118 further comprises a first pull-up p-type field effect transistor (PFET) 106 containing a third drain, which is physically a third active area, and a second pull-up PFET 106′ containing a fourth drain, which is physically a fourth active area. Each of the source/drain nodes of the pass gate transistors (102, 102′) may function as a source or a drain depending on the operation of the SRAM circuit.
The third active area is electrically connected to the first active area via a collection of a first contact via, a first M1 wire, and a first CA bar. This connection is represented in the circuit schematic 118 by a first internal node 111. Similarly, the fourth active area is electrically connected to the second active area via a collection of a second contact via, a second M1 wire, and a second CA bar. This connection is represented in the circuit schematic 118 by a second internal node 111′. The gates of the second pull-up PFET 106′ and the second pull-down NFET 104′ are adjoined to the third drain of the first pull-up PFET 106 via the first CA bar. This connection is represented in the circuit schematic 118 by a third internal node 113A and a fourth internal node 113B. The gates of the first pull-up PFET 106 and the first pull-down NFET 104 are adjoined to the fourth drain of the second pull-up PFET 106′ via the first CA bar. This connection is represented in the circuit schematic 118 by a fifth internal node 113A′ and a sixth internal node 113B′. The internal nodes (111, 111′, 113A, 113B, 113A′, 113B′) are connected by CA contact vias 176 and CA bars 178 as well as M1 wires 188. Bit line wiring (115, 115′) and word line wiring (117, 117′) are typically implemented at M2 and M3 levels.
Dimensions of semiconductor devices continue to shrink as scaling of semiconductor device continues. As features sizes are reduced relative to the wavelength of lithography tools, which may be 193 nm for ArF excimer ultraviolet radiation or 157 nm for F2 laser, optical proximity effects cause printing of a complex pattern difficult. Specifically, a jog in width in an area at which the second width W2 changes into the first width W1 causes rounding of edges and tapering of the width of the planar pass gate transistors (112, 112′) and the pull-down transistors (114, 114′). Even optical proximity correction (OPC) tends to be unable to eliminate such rounded features, and consequent uncertainty of the width of the transistors under the gate electrodes 132. Thus, the change in the width of the combined active area of each of the planar pass gate transistors (112, 112′) and one of the pull-down transistors (114, 114′) adjoined thereto invariably causes adverse impacts on variability and/or predictability of the on-currents of the transistors, and consequently to the beta ratio and to SRAM cell stability.
In view of the above, there exists a need for an SRAM cell structure providing a stable beta ratio and high cell stability, and methods of manufacturing the same.
Further, there exists a need for an SRAM cell structure conducive to printing of an active area image of high optical fidelity with well defined width for the gate of pass transistors and pull-down transistors, and methods of manufacturing the same.